1. Field of the Invention
The present invention relates to a phase lock loop device, and in particular relates to a phase lock loop device capable of alleviating degradation due to charge pump mismatch.
2. Description of the Related Art
FIG. 1 is a function block diagram showing a conventional phase lock loop (PLL) device 100 for carrying out data clock recovery. The PLL device 100 comprises a phase detection (PD) device 102, a charge pump and loop filter (CPLF) device 104, a voltage control oscillator (VCO) 106 and a D-type flip-flop (DFF) 108.
The phase detection device 102 detects the transition of each input data datain, outputting an up-index UP when the transition edge of the input data leads a clock signal CK and outputting a down-index DN when the transition edge of the input data lags the feed-back clock signal CK. If there is no phase difference between the input data datain and the clock signal CK, the phase detection device 102 doesn't output up-index UP or down-index DN. Generally, the clock signal CK general is fed back to the phase detection device 102 through a division device (not shown in FIG. 1), and here the division device is supposed to carry out a divide-by-one operation for brevity.
The CPLF device 104 comprises a charge pump and a loop filter (both not shown in FIG. 1), implemented by current switches, resistors, capacitors or active devices. The function of the CPLF device 104 can be analyzed as a combination of a proportional path CP1 and an integration path CP2, and the combination may be an adding operation. The CPLF device 104 adjusts its output voltage Vc according to the received up-index UP or down-index DN.
The VCO 106 outputs the clock signal CK and changes the frequency of the clock signal CK according to the voltage Vc outputted from the CPLF device 104.
The D-type flip-flop 108 samples the input data datain according to the clock signal CK, and outputs the data dataout.
Gain mismatching of internal circuitry is unavoidable when implementing the charge pump in the CPLF device 104, and therefore the PLL device 100 can not ideally lock the clock signal CK when performing data clock recovery.